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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Suppose I've to transfer data from clk domain to clk/2 then PLL can help reduce the skew on the clk/2, right?

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That is correct.

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I've added a picture to visualize the problem.

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The picture doesn't match your description. According to the picture, you are not dividing by 2. And what is more important, you are muxing between two clocks, which is quite a different issue. So please let us know exactly what you want to do.