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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Do you actually need to use clk/2 as a clock in your design? Won't a clock enable work as well? With the "ripple" clock, even if Quartus will be able to achieve timing closure, you considerably restrict the fitter in achieving optimal timing in other parts of the design and at least increase synthesis effort.