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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As far as you described the problem, I don't think that using a PLL for the clock divider would bring an actual benefit. PLL is mandatory, if e.g. generating multiple clocks with well defined phase relation.