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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Sorry, I take it back. I missed this in the Stratix III manual 

Stratix III device PLLs cannot be driven by internally generated GCLKs or RCLKs. 
The input clock to the PLL must come from dedicated clock input pins/PLL-fed 
GCLKs or RCLKs only.

So, I'm left with using a logic divider for the clock.