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I'm using Stratix III device. I didn't see any restriction on the logic driving the GCLK line (which can feed a PLL).
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I think that actually,
no Altera FPGA family allows this. PLLs
can't be driven (directly or indirectly) from a general purpose I/O pin.
Newer families allow the PLL to be driven from a clock control block, but
only when the clock control block is driven by a dedicate clock pin, or by the output of another PLL.
As the quote above from the CIII handook, internally generated signals can't drive a PLL. But it is even worst (that handbook is not complete), general purpose I/O pins can't drive PLLs either. This is missing in the CIII handbook, but it is mentioned in other ones (at least I can see it in the SIV handbook).
In other words, you are correct that there is no restriction to drive the GCLK, but this is true only
as long as you don't try to drive a PLL from it.
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