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Altera_Forum
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15 years ago

PLL input from non-dedicated clock pin

Hello all, I've struck with a simple problem and I'm almost nearing the wall in terms of options. I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm using Stratix III device. I didn't see any restriction on the logic driving the GCLK line (which can feed a PLL).

There are clock muxes (2:1) in the design with each clock being gated before it is fed to the mux. I saw the clock gating is not being turned into register enable. So, I will have to generate the divide-by-2 clock.

Thanks,

Gopal