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Altera_Forum
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17 years ago

PLL generated clocks and timing constraints

Is there a way to specify a tco from a clock generated by a pll to an output pin? The Quartus manual says that tco only defines a pin to pin delay, but this clock does not come from a pin. Also, fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yeah, that's a weird combo, and assume anything this domain needs to be related to is out of the PLL. If I remember correctly, your Tco is still your delay from the input pin to/through the PLL, minus it's delay compensation, plus the global, through the register and out the pin. The compensation and global should be pretty close to canceling out.

Again, since your Tco's don't really make sense in relation to your input clock, that delay will just cancel out for everything you do.