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Altera_Forum's avatar
Altera_Forum
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17 years ago

PLL Compensation warning

Hi All,

I have a source synchronous interface where the received clock is driving a dedicated PLL clock input and the PLL being instantiated is configured for source synchronous mode. I've also set the PLL_COMPENSATE assignment on the data input bus pins. The C0 output from the PLL (with no phase adjustment) is directly clocking a megawizird generated ALT_DDIO block, that is also fed by the above mentioned data bus.

I'm receiving the following warning though from the fitter:

Warning: PLL <removed> in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register

For the life of me I don't see why I'm getting this error. Is the ALT_DDIO block not being placed in flops next to the I/O? I'd appreciate it if anyone has any thoughts on this.

Raphael

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Ok, I found the issue. As I suspected, the ALTDDIO megafunction is not implemented with registers in the I/O.

    From the device handbook:

    -------------------

    The DDR input registers are implemented with three internal logic element (LE)

    registers for every DQ pin. These LE registers are located in the logic array block (LAB) adjacent to the DDR input pin.

    thanks,

    Raphael