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Altera_Forum
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16 years ago

PLL Compensation warning

Hi All, I have a source synchronous interface where the received clock is driving a dedicated PLL clock input and the PLL being instantiated is configured for source synchronous mode. I've also se...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Ok, I found the issue. As I suspected, the ALTDDIO megafunction is not implemented with registers in the I/O.

From the device handbook:

-------------------

The DDR input registers are implemented with three internal logic element (LE)

registers for every DQ pin. These LE registers are located in the logic array block (LAB) adjacent to the DDR input pin.

thanks,

Raphael