ContributorHi
Is there an option to generate clock by PLL like as clock gate ?
for example :
ref clock = 128Mhz
output clock = 120Mhz
waveform :
Meaning , clock 120Mhz behave like 128Mhz but without 1 clock that missing
Regular ContributorHello,
Perhaps you can refer to this design example:
Regards,
Aqid
Super ContributorHi,
the Stratix 10 design example uses PLL-reconfiguration to switch clocks on and off. That's quite different from the intended function.
As far as I see, PLL's have no features to manipulate waveforms on a cycle-by-cycle basis. The intended waveform can be however easily obtained with regular clock gating techniques in logic cells, as suggested in Quartus handbook:
Generating gated clocks in FPGA makes only sense if you want to feed external logic. Internally gated clocks should be converted into clock enables.
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