Please help to fix the errors

Hello,

When I run the code, I got these errors:

Error (10476): VHDL error at controller.vhd(105): type of identifier "max_add" does not agree with its usage as "std_logic_vector" type

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

The code is Here:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity controller is

generic

(WORD_SIZE :Natural :=8;

RAM_DEPTH :Natural :=32;

ADDRESS_LENGTH :Natural :=5);

port

(test_data : in std_logic_vector(WORD_SIZE-1 downto 0);

config_in : in std_logic_vector(WORD_SIZE-1 downto 0);

clk : in std_logic;

nrst : in std_logic;

config : in std_logic;

check : in std_logic;

max_add : in std_logic_vector(ADDRESS_LENGTH-1 downto 0);

mx_add : in std_logic;

samp_out : in std_logic_vector(WORD_SIZE-1 downto 0); --from ram

samp_in : out std_logic_vector(WORD_SIZE-1 downto 0); --to ram

test_en : out std_logic;

test_rdwr : out std_logic;

test_add : out std_logic_vector(ADDRESS_LENGTH-1 downto 0);

test_ok : out std_logic;

see_result : out std_logic;

samp_add : out std_logic_vector(ADDRESS_LENGTH-1 downto 0);

samp_en : out std_logic;

samp_rdwr : out std_logic;

seg_addr : out std_logic_vector(ADDRESS_LENGTH-1 downto 0));

end controller;

architecture BEHAVIOR of controller is

type mem is array (0 to RAM_DEPTH-1) of std_logic_vector(WORD_SIZE-1 downto 0);

signal memory: mem;

type states is (sidle,sconfig,scheck,scompare);

signal state :states;

function CONV_STDLOGICVECTOR(X:INTEGER; SIZE:INTEGER)

return STD_LOGIC_VECTOR IS

Variable RESULT:STD_LOGIC_VECTOR(SIZE-1 downto 0);

Variable TEMP :INTEGER;

begin

if X<0 then

TEMP:=(2**RESULT'LENGTH)+X;

else

TEMP:=X;

end if;

for i in RESULT'REVERSE_RANGE loop

case TEMP mod 2 is

when 0=>RESULT(i):='0';

when 1=>RESULT(i):='1';

when others=>null;

end case;

TEMP:=TEMP/2;

end loop;

return RESULT;

end;

begin

process(clk,nrst,config,check)

variable sample_count:natural;

variable tested_count:natural;

variable success_count:natural;

variable fail_count:natural;

variable max_add:natural;

variable mx_add:natural;

variable address:std_logic_vector(ADDRESS_LENGTH-1 downto 0);

variable test_address:std_logic_vector(ADDRESS_LENGTH-1 downto 0);

variable saddress_rdptr:natural;

variable saddress_wrptr:natural;

variable taddress_ptr:natural;

begin

if(nrst='0')then

for i in 0 to RAM_DEPTH-1 loop

memory(i)<=(OTHERS=>'0');

end loop;

sample_count :=0;

success_count:=0;

fail_count :=0;

state <= sidle;

samp_en <='0';

test_en <='0';

test_ok <='0';

see_result <='0';

test_rdwr <='0';

test_add <= (OTHERS =>'0');

mx_add := 0;

elsif(clk='1' and clk'event)then

case state is

when sidle =>if (config='1')then

samp_en <='1';

samp_rdwr <='1';

samp_add <=conv_stdlogicvector(saddress_wrptr,ADDRESS_LENGT H);

samp_in <=config_in;

state <= sconfig;

--saddress_wptr:=saddress_wptr+1;

elsif(check='1')then

if(taddress_ptr=conv_integer(max_add))then

state <= sidle;

else

mx_add:=CONV_INTEGER(max_add);

samp_en<='1';

samp_rdwr<='0';

address := (OTHERS=>'0');

test_en <='1';

test_rdwr <='0';

test_add <=(OTHERS=>'0');

samp_add <= address;

taddress_ptr :=taddress_ptr + 1;

state <= scheck;

end if;

end if;

when sconfig =>if(config='1')then

saddress_wrptr :=saddress_wrptr+1;

address :=conv_stdlogicvector(saddress_wrptr,ADDRESS_LENGT H);

samp_add <=address;

samp_in <= config_in;

samp_en <= '1';

samp_rdwr <='1';

state <=sconfig;

else

state <= sidle;

memory(sample_count) <=conv_stdlogicvector(saddress_wrptr-1,WORD_SIZE);

sample_count :=sample_count +1;

end if;

when scheck => samp_en <='1';

samp_rdwr <='0';

test_en <='1';

test_rdwr <='0';

if (samp_out/=test_data) then

fail_count :=fail_count + 1;

else

success_count :=success_count +1;

end if;

if(taddress_ptr=conv_integer(max_add)) then

state <= scompare;

tested_count :=tested_count +1;

else

state <= scheck;

saddress_rdptr :=saddress_rdptr + 1;

taddress_ptr :=taddress_ptr +1;

address := conv_Stdlogicvector(saddress_rdptr,ADDRESS_LENGTH) ;

test_address :=conv_stdlogicvector(taddress_ptr,ADDRESS_LENGTH) ;

sam_add <= address;

test_add <= test_address;

end if;

when scompare =>if(success_count >=fail_count)then

test_ok <='1';

see_result <='1';

seg_addr <=conv_stdlogicvector(saddress_rdptr,ADDRESS_LENGT H);

state <=sidle;

else

if(trsted_count = sample_count)then

test_ok <='0';

see_result <='1';

state <=sidle;

else

test_ok <='0';

see_result <='0';

state <=scheck;

saddress_rdptr:=(conv_integer(memory(tested_count) +1));

samp_add <=conv_stdlogicvector(saddress_rdptr,ADDRESS_LENGT H);

samp_en <='1';

test_en <='1';

tested_count := tested_count +1;

test_add <=(others =>'0');

end if;

end if;

end case;

end if;

end process;

end BEHAVIOR;

Thank you in advance