Please Help!!!! I am receiving the error "error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 6 us". My code is as given below . I am trying to make ALU multiplier.

module mrl(a,b,res,rs);

input [3:0]a;

input [3:0]b;

output [5:0]res;

output rs;

reg overflow;

reg [2:0]r;

reg [1:0]sum;

reg [2:0]cb;

reg [1:0]carry;

integer ii;

always @(a[1] || a[2] || a[3] || a[0] || b[0] ||b[1]||b[2]||b[3])

begin

sum[0]=1'b1;

sum[1]=1'b1;

end

always @(*)

begin

cb[0]=b[0];

cb[1]=b[1];

cb[2]=b[2];

for(ii=0; ii<3; ii=ii+1)

begin

if(cb[0]==1'b1)

begin

r[0] = a[0]^r[0]^~cb[0];

carry[0] = (a[0]&r[0])|(r[0]&~cb[0])|(~cb[0]&a[0]);

r[1] = a[1]^r[1]^carry[0];

carry[1] = (a[1]&r[1])|(r[1]&carry[0])|(carry[0]&a[1]);

r[2] = a[2]^r[2]^carry[1];

overflow = (a[2]&r[2])|(r[2]&carry[1])|(carry[1]&a[2]);

end

cb[2]=cb[1];

cb[1]=cb[0];

cb[0]=r[2];

r[2]=r[1];

r[1]=r[0];

r[0]=overflow;

overflow=1'b0;

end

end

assign rs=a[3]^b[3];

assign res[0]=r[0];

assign res[1]=r[1];

assign res[2]=r[2];

assign res[3]=cb[0];

assign res[4]=cb[1];

assign res[5]=cb[2];

endmodule