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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Platform designer very slow when opening top level system (21.1 Std)

Hello, I am currently working on a FPGA project with the Quartus Prime Standard 21.1 software. When opening the top level QSYS-file it takes forever to finally finish (multiple hours). I have test...
Compilation
Hdl
Platform
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Unfortunately, I don't think it is possible to instantiate a pre-compiled IP core in Platform Designer (Standard).


The Platform Designer (Standard) tool saves both component instantiation and system interconnects in a single .qsys file. On the other hand, Platform Designer Pro features hierarchical isolation between system interconnect and IP components. This is achieved by saving the parameters of each IP component in a .ip file, while the system interconnect is saved in a .qsys file.


Best Regards,

Richard Tan