ContributorPlatform designer testbench PLL component does not match entity
I am using Quartus 18.0 and generating testbench from the Platform designer (aks Qsys) system.
The Qsys system contains a PLL. When I generate testbench files, the list contains a .vho and a .vo file. One contains the PLL entity (VHDL) while the other contains the PLL module (Verilog). The input signals in both these files have no default values. Qsys usually likes to assign default values to input ports in RTL code.
The problem is that when I try to compile the simulation files, it fails. The source of the problem is how the component declaration and portmap has been done between the synthesis and simulation top level .vhd file.
The synthesis file component declaration in top level file is:
component S_PLL is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c2 : out std_logic; -- clk
scandone : out std_logic; -- export
scandataout : out std_logic; -- export
c1 : out std_logic; -- clk
c3 : out std_logic; -- clk
c4 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic; -- export
phasecounterselect : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
phaseupdown : in std_logic := 'X'; -- export
phasestep : in std_logic := 'X'; -- export
scanclk : in std_logic := 'X'; -- export
scanclkena : in std_logic := 'X'; -- export
scandata : in std_logic := 'X'; -- export
configupdate : in std_logic := 'X' -- export
);
end component S_PLL;This changes in the simulation top level file to:
component S_PLL is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c2 : out std_logic -- clk
);
end component S_PLL;Why are they different? Compiling simulation files fails because the component is missing many ports.
