Platform designer testbench PLL component does not match entity

If we change the synthesis files to Verilog, the same issue is observed:

Synthesis top level:

 SPRINT_OSI_S_PLL pll (
  .clk               (clk_33m_clk),                              //      inclk_interface.clk
  .reset             (rst_controller_reset_out_reset),           // inclk_interface_reset.reset
  .read              (mm_interconnect_0_pll_pll_slave_read),     //            pll_slave.read
  .write             (mm_interconnect_0_pll_pll_slave_write),    //                     .write
  .address           (mm_interconnect_0_pll_pll_slave_address),  //                     .address
  .readdata          (mm_interconnect_0_pll_pll_slave_readdata), //                     .readdata
  .writedata         (mm_interconnect_0_pll_pll_slave_writedata), //                     .writedata
  .c0                (pll_c0_clk),                               //                   c0.clk
  .c2                (pll_c2_clk),                               //                   c2.clk
  .scandone          (),                                         //          (terminated)
  .scandataout       (),                                         //          (terminated)
  .c1                (),                                         //          (terminated)
  .c3                (),                                         //          (terminated)
  .c4                (),                                         //          (terminated)
  .areset            (1'b0),                                     //          (terminated)
  .locked            (),                                         //          (terminated)
  .phasedone         (),                                         //          (terminated)
  .phasecounterselect (3'b000),                                   //          (terminated)
  .phaseupdown       (1'b0),                                     //          (terminated)
  .phasestep         (1'b0),                                     //          (terminated)
  .scanclk           (1'b0),                                     //          (terminated)
  .scanclkena        (1'b0),                                     //          (terminated)
  .scandata          (1'b0),                                     //          (terminated)
  .configupdate      (1'b0)                                      //          (terminated)
 );

Simulation top level

 SPRINT_OSI_S_PLL pll (
  .clk      (clk_33m_clk),                              //      inclk_interface.clk
  .reset    (rst_controller_reset_out_reset),           // inclk_interface_reset.reset
  .read     (mm_interconnect_0_pll_pll_slave_read),     //            pll_slave.read
  .write    (mm_interconnect_0_pll_pll_slave_write),    //                     .write
  .address  (mm_interconnect_0_pll_pll_slave_address),  //                     .address
  .readdata (mm_interconnect_0_pll_pll_slave_readdata), //                     .readdata
  .writedata (mm_interconnect_0_pll_pll_slave_writedata), //                     .writedata
  .c0       (pll_c0_clk),                               //                   c0.clk
  .c2       (pll_c2_clk)                                //                   c2.clk
 );