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gyuunyuu's avatar
gyuunyuu
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6 years ago

Platform designer testbench PLL component does not match entity

I am using Quartus 18.0 and generating ​testbench from the Platform designer (aks Qsys) system. The Qsys system contains a PLL. When I generate testbench files, the list contains a .vho and a .vo fi...
gyuunyuu's avatar
gyuunyuu
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6 years ago

This is clearly a bug in Qsys. The only method to solve this at present would be to force the Qsys to make these ports visible.

I had a similar problem before where no VHDL files were being generated at all. I uninstalled and reinstalled Quartus and the problem went away.

If you can't see this problem on your end then this case should be closed as it is.