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PZ25's avatar
PZ25
Icon for New Contributor rankNew Contributor
2 years ago

Platform Designer: HDL blackbox automapping feature erroneous

Hello

I try to import a core partition into my projects platform designer having a number of AXI MM and streaming I/F. I named the VHDL ports according to the conventions for automapping noted in

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/name-hdl-signals-for-automatic-interface.html

However, all AXI I/F are importet as "streaming", even the memory mapped ones, resulting in wrong assignments.

Is there an addtional rule that separates MM from streaming?

Best reagrds,
Peter

Platform

3 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Can you show your port HDL? Something else must be going on here.

    Also, I presume this is happening even after analyzing the HDL file(s) on the Files tab of the Component Editor?

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Could you please try changing the Interface Type to your required setting and check if any error messages appear that might provide a clue?

    Best Regards,

    Richard Tan

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transition your inquiry to our community support.

    We apologize for any inconvenience this may cause and we appreciate your understanding.

    If you have any further questions or concerns, please don't hesitate to let us know.

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    Best Regards,

    Richard Tan