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New ContributorPlatform Designer: HDL blackbox automapping feature erroneous
Hello
I try to import a core partition into my projects platform designer having a number of AXI MM and streaming I/F. I named the VHDL ports according to the conventions for automapping noted in
However, all AXI I/F are importet as "streaming", even the memory mapped ones, resulting in wrong assignments.
Is there an addtional rule that separates MM from streaming?
Best reagrds,
Peter
3 Replies
sstrellSuper Contributor
Can you show your port HDL? Something else must be going on here.
Also, I presume this is happening even after analyzing the HDL file(s) on the Files tab of the Component Editor?
- RichardT_altera
Could you please try changing the Interface Type to your required setting and check if any error messages appear that might provide a clue?
Best Regards,
Richard Tan
- RichardT_altera
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