Place region and Route region of Quartus Partial Reconfiguration
I've noticed that there are "Place region" and "Route region" in Quartus Partial Reconfiguration(PR).
I have three related questions.
1) Is the PR persona's routing fully encapsulated in the Route region?
2) There exist "Reserved Placement" and "Reserved Routing" in Logic Lock Regions Properties window as shown below.
If the Place region and Route region are identical (without any Route region's expansion),
"Reserved Routing" setting below is inferred, right?
EDIT: In fact, "Reserved Routing" setting, which creates
RESERVE_ROUTE_REGION ON in the .qsf file, seems to do something different from
the description above because I gave it a try and the routing phase takes more than 30 min(still not finished)
for the design that took 3 min for routing before.
What does RESERVE_ROUTE_REGION ON exactly do?
3) The static design can use routing resources in the PR regions, right?
(I am not sure this is explicitly stated in the PR user guide.)
Is there any simple setting that we can prevent the static design to borrow even the routing resources in the PR region so that static design and PR Personas are isolated?
I am kind of new to Intel FPGA, but this forum has been very helpful. Thanks.