PISO reg issue

Hi,

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If i simply wrote if (sclk_adc) ... else... my shift regs will load with main clock since this block is posedge clk_i, so i created pos and neg edge detectors which work well enough, but they latched on the next clk after pos_sclk detected, why?

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It seems to be latched on the next clk after pos_sclk detected but if you check carefully the posedge clk_i & posedge reset wave then you we will reliase that it is looking for posedge clk_i or posedge reset event when pos_sclk is High.

Refer the yellow colored cursor portion in the attached screenshot.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)