That was helpful!
But i faced another problem with those shift regs :c
module shiftreg1 (
input reset,
input clk_i,
output sclk_adc,
input din,
output dout
);
reg counter = 0;
reg shiftOut = 16'b1000_1000_1000_1000;
wire out_next;
//
assign sclk_adc = counter;
reg curr_in = 0;
wire shiftIn = {curr_in, din};
assign dout = shiftOut ;
assign out_next = { shiftOut, 1'b0};
reg main_reg;
wire pos_sclk, neg_sclk;
assign pos_sclk = sclk_adc & ~main_reg;
assign neg_sclk = ~sclk_adc & main_reg;
////////////////////////////
always @(posedge clk_i or posedge reset)
begin
counter <= counter +1;
main_reg <= sclk_adc;
if (pos_sclk)
begin
shiftOut <= out_next;
end
if (neg_sclk)
begin
curr_in <= shiftIn;
end
end
endmodule
So, i generated slow clock sclk_adc from main clock, and then need to load regs within posedge and negedge of this sclk_adc. If i simply wrote if (sclk_adc) ... else... my shift regs will load with main clock since this block is posedge clk_i, so i created pos and neg edge detectors which work well enough, but they latched on the next clk after pos_sclk detected, why?
in this matter change in block/non-block assignments does not affect answer. pls help me to explain this
is there any way to avoid creating a new always (with sclk_adc event there) blocks?
https://www.alteraforum.com/forum/attachment.php?attachmentid=15845
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