Honored ContributorHello, I ahave a general question about how the compiler will place pipeline registers.
If I design a complex logic circuit that I want to pipeline, can I place pipeline registers at the output of the circuit and expect that the compiler will optimize the placement in the circuit, or do I manualy have to place them in to the circuit?
Honored ContributorHi,
Sorry but I didn't get what exactly you have in mind but I think you have to manually add the pipline registers. For example if you have a signal: wire output_signal; You can add pipline register: reg pipline_reg_out; always @(posedge clock)pipline_reg_out <= output_signal;
This will optimize the the timings. Of course the trade off is with one clock cycle delay.
Honored ContributorYes, I know that I manualy has de add the registers. The question is where to place them?
Do I need to manualy have to place them where I expect that the critical path will be? like this: process(clock) begin if rising_edge(clock) then pipe1 <= some long expression( input ); pipe2 <= another long expression( pipe1 ); end if; end process; or? can I just add registers at the end of an exspression and expect that the compiler will optimize the placement, like this: process(clock) begin if rising_edge(clock) then pipe1 <= another long expression( some long expression( input ) ); pipe2 <= pipe1; end if; end process;Honored ContributorYou should manually place them where you would expect critical path. The second example will need timings for both expressions. Try synthesizing the expressions in simple project and see the difference in path timings.
Best regards, VTHonored ContributorWell I can tell you from own experience that Xilinx ISE does what you want. I think Quartus II does it too, but I'm not sure, simply test it and take a look at the Schematic result after fiting.
Honored ContributorYes, it will.
Lookup register retiming in the manual.Honored Contributorrbugalho is right, Register Retiming is what you need to enable:
http://www.altera.com/literature/hb/qts/qts_qii52007.pdf i've played with this before adding extra registers before the logic instead of after. i can't remember if it works putting them after, you'll have to test it out. i also found that adding multiple registers did not always yield the best results, so you should do some experiment to see what works best for each circuit. i haven't tried this in the most recent version of Quartus, its possible the algorithm has improved.
