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FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
2 years ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
12 months ago

This info is all in the timing reports you posted. The waveform view clearly shows that you are analyzing timing with the launch edge as the falling edge. The setup slack report shows a clock skew of over 2.2 ns for all the failing paths listed in red. I'm also not sure what you are trying to accomplish with the multicycle timing exceptions in your SDC.