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FPGA_Newbie
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2 years ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
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FPGA_Newbie
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12 months ago

Hey sstrell,

i didn't understand what you meant with the launching and latching edge, but i got it now, i should initialise "clk_2" with '0' not '1'.
where can i see that i have a clock skew ?