Forum Discussion

FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
1 year ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

It's really not clear what you are trying to do here. You're launching on a falling edge and latching an output (to a downstream device I presume) on the following launch edge, so you only have 4 ns between launch and latch. Is that intended?

You also have a huge clock skew. I'm not really sure what is going on here.