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FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
2 years ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
12 months ago

It's really not clear what you are trying to do here. You're launching on a falling edge and latching an output (to a downstream device I presume) on the following launch edge, so you only have 4 ns between launch and latch. Is that intended?

You also have a huge clock skew. I'm not really sure what is going on here.