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FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
2 years ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
I have a comment beyond LPM_divide maximum speed question. I'm frequently implementing RMS measuring circuits, I wonder why you don't use a topology without divider. I have however difficulties to relate your RTL schematic to a usual RMS scheme which is either fixed integration window over n periods of signal fundamental or continuous recursive processing with low pass (equivalent of analog RMS detector circuit). In case of discontinuos processing, division is only performed once per window period or substituted by a multiply.