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FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
1 year ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

I can see that there is significant clock skew and possibly a large data delay, which might be causing the issue.

Please check the data path to see if there is a high fanout or a point where there is a substantial delay.


Could you share your design by archiving the project (Project > Archive Project) so that I can investigate it further.


Regards,

Richard Tan