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FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
1 year ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

There's still more of the data arrival path that you have not shown. What you have shown does not show the significant delay that may be causing the issue. Scroll down to show the rest.

And it would help to show your .sdc. Multicycle can easily screw things up if you don't use it properly.