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FPGA_Newbie's avatar
FPGA_Newbie
Icon for New Contributor rankNew Contributor
1 year ago

Pipeline parameter issues for LPM_Divide

Hey everyone, im new to VHDL and Quatus Prime. Im working with ADC data and i need to calculate the RMS for it using LPM_Mult, LPM_Divide and ALTSQRT, but im having problems with pipeline values ...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

It's not clear that pipelining has anything to do with it. You have over 4 ns of data delay on this failing path. What would be really useful to see is the data arrival path section of that report to see where that extensive data delay is coming from. Also, make sure that your design is fully constrained for timing. Seeing your .sdc file would be useful as well.