Honored ContributorThis should be really simple. I'm new at this. Why do I get a compile message, "output stuck at ground"? I just want to generate a stretched pulse when I get a nWR low edge.
module Extend_nWR ( input clk, input nWR, output xWR ); reg temp; always @ ( negedge nWR ) begin temp = 1'b1; # 4 temp = 1'b0; end assign xWR = temp; endmodule
Honored ContributorTime delays (#) are not synthesisable. The last assignment is 0, hence stuck at ground. If you want a stretch pulse, you need to use a counter.
Honored ContributorHonored ContributorThe quartus manual provides plenty of into on how to synthesize the different logic elements for the fpga. And altera provides plenty of tutorials. And there are many other tutorials and textbooks too.
Honored ContributorHi Dank,
I could suggest you add in the reset signal to initial this reg. this is will be undefined.
