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Altera_Forum
Honored Contributor
Honored ContributorPin "x" is stuck at GND
This should be really simple. I'm new at this. Why do I get a compile message, "output stuck at ground"? I just want to generate a stretched pulse when I get a nWR low edge.
module Extend_nWR ( input clk, input nWR, output xWR ); reg temp; always @ ( negedge nWR ) begin temp = 1'b1; # 4 temp = 1'b0; end assign xWR = temp; endmodule4 Replies
Altera_ForumTime delays (#) are not synthesisable. The last assignment is 0, hence stuck at ground. If you want a stretch pulse, you need to use a counter.
- Altera_Forum--- Quote Start --- Time delays (#) are not synthesisable. The last assignment is 0, hence stuck at ground. If you want a stretch pulse, you need to use a counter. --- Quote End --- Thanks! Will search/post separately asking for leads on good basic info, like what is sythesizable. Am interested in good starting points - I'm an EE with lots of embedded experience and just starting FPGA. Amazed at how little good practical instruction there is online.
- Altera_Forum
The quartus manual provides plenty of into on how to synthesize the different logic elements for the fpga. And altera provides plenty of tutorials. And there are many other tutorials and textbooks too.
- Altera_Forum
Hi Dank,
I could suggest you add in the reset signal to initial this reg. this is will be undefined.
