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Altera_Forum's avatar
Altera_Forum
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12 years ago

Pin planner

Hi ,

At the Pin planner , i configure the I/O standard,slew rate , current strength for each pin .

at the .qsf file - new lines were created by my choices .

i know that the voltage,current,slew rate is fixed for each pin according to his hardware properties , so what does those new lines changes ?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    i know that the voltage,current,slew rate is fixed for each pin according to his hardware properties , so what does those new lines changes ?

    --- Quote End ---

    Not quite right.

    I/O voltage is set by VCCIO connection and you need to inform Quartus about this choice in the Pin Planner. But current or slew rate are programmable for most FPGA families. Review the device handbook.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi ,

    i read at the device handbook that the current strength and slew rate ate programmable i didn't understand if the voltage change due to yhe selection .

    F.E : if the bank connected to V=3[v] and i choose to configure the pin to 2.5[v] - does it means that the output voltage will be 2.5[v] ?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You are expected to select an I/O standard that fits the applied VCCIO value. Selecting an incompatible I/O standard doesn't change the voltage but might cause I/O failure.