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Altera_Forum's avatar
Altera_Forum
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16 years ago

pin planner error:can't place PLL

Hi all,

I have a problem about pin planner when i use quartusii, it shows :can't place PLL"CLOCK:inst9|altpll_component|CLOCK_altpll:auto_generated|pll1"--I/Opin LVDS_CLK(port type INCLK of the PLL)is assigned to a location which is not connected to port type INCLK of any PLL on the device.

I don't know the meaning. Can somebody help me?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Hi all,

    I have a problem about pin planner when i use quartusii, it shows :can't place PLL"CLOCK:inst9|altpll_component|CLOCK_altpll:auto_generated|pll1"--I/Opin LVDS_CLK(port type INCLK of the PLL)is assigned to a location which is not connected to port type INCLK of any PLL on the device.

    I don't know the meaning. Can somebody help me?

    --- Quote End ---

    Hi,

    I assume you have your clock signal to a pin assigned, which could not routed to a PLL.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Thanks!

    I changed a diffio pair to that pin, compilation passed!

    thanks!