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Altera_Forum's avatar
Altera_Forum
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17 years ago

Pin assignment

Hello,

I'm implementing a soft-core processor in Altera Cyclone.My top level design entity is zpu_core_small.vhd which is the main programm of the processor.I have other files e.g uart.vhd in order to connect to the serial RS232. My problem is, i can't find the inputs of uart.vhd in the node name of pin planner.I need that in order to assign the necessary input with Tx from FPGA.In the pin planner, the node name list only the inputs and outputs of zpu_core_small.vhd. Any hints???

Help will be greatly appreciated

Regards,

Bruno

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If uart.vhd is a sub component of zpu_core_small.vhd then the Rx and Tx pins of the UART sub module should be wired internally to the top level. Pins only exist for the top level component.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Yes, as very basic feature of any HDL design, the FPGA is only exposing pins included in the design top port definition. Components defined in other design files must be instantiated in the top design and connected to the top level port by interface signals, if necessary.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thx..the problem now is how i can connect the uart.vhd with my top-level-design entity??

    can you give me example?? link or whatsoever..
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You have to create a higher level design file (may be a vhd file or a bdf schematic file) in which you have to recall your current top-level file and the uart.vhd, of course defining the connection between their IN/OUT signals.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thx!!

    i got what you mean..i've created symbol files for both uart.vhd and my top-level design entity.I created new .bdf project and put the 2 newly created symbols file together in my new .bdf project.This .bdf project is the the new top-level design entity.