Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- How exactly did you assign this value to your gain/ref? If Quartus asks you to assign your gain signals to FPGA pins, it means that you connected your gain signal to ports on the top level HDL file. In that case the value you assigned will be ignored by Quartus, and the voltage level on those pins will be used instead. What you need to do is disconect your gain/ref signal from any ports on the top level file and assign it to a constant value there. --- Quote End --- Do take port B out during mapping of the comparator???