pin assignment - unused GPIO pins

You have two options;

1. Define all pins used in a schematic as port in your top-level HDL file, and drive them with valid values.

2. Use the device option to "tri-state unused pins", or "enable weak pull-up on unused pins"

Given that a design may not use all FPGA pins on a device, I generally use both options.

Run the scripts associated with this DE0-nano design

http://www.alteraforum.com/forum/showthread.php?t=45927

and you'll see an example of;

1. A top-level design file that includes all I/O pins used on the DE0-nano board

2. A constraints.tcl script that assigns all the pins on the top-level, and some default constraints (including the weak pull-ups on unused pins constraint).

3. A synthesis script synth.tcl that automates the build.

This approach allows me to create a new project by copying the top-level HDL and synth.tcl script, making a few minor path adjustments for the new project, and then synthesize a new design.

I never have to worry about whether I have forgotten to assign pins correctly.

Cheers,

Dave