PCIe IP example error: Failed to open design unit file "../../../top_core.vo" in read mode.

I tried shortening the directory to which Quartus restores the .qar file to just "D:/c/", but I still get this error:

# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016

# Start time: 23:43:27 on Jul 30,2019

# vlog -reportprogress 300 "+incdir+../../common/testbench/+../../common/incremental_compile_module+.." -work work ../../../top_core.vo

# ** Error: (vlog-7) Failed to open design unit file "../../../top_core.vo" in read mode.

# No such file or directory. (errno = ENOENT)

# End time: 23:43:27 on Jul 30,2019, Elapsed time: 0:00:00

# Errors: 1, Warnings: 0

# ** Error: D:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.

# Error in macro ./runtb.do line 115

# D:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vlog failed.

# while executing

# "vlog +incdir+../../common/testbench/+../../common/incremental_compile_module+.. -work work $vfile"

# ("while" body line 2)

# invoked from within

# "while {[gets $simlist vfile] >= 0} {

# vlog +incdir+../../common/testbench/+../../common/incremental_compile_module+.. -work work $vfile

# }"

# ("eval" body line 3)

# invoked from within

# "_comp"

anything else i can try? can you send me the correct top_core.vo file directly?