PCIe Compiler Serdes pll

You'll have to alter two files :

<variation>_serdes.vhd

...
signal_detect_hysteresis => 4,
signal_detect_hysteresis_valid_threshold => 14,
signal_detect_loss_threshold => 3,
...

<variation>_examples\chaining_dma\db\altpll_sc81.tdf

...
VARIABLE 
	pll1 : cycloneiv_pll
		WITH (
			BANDWIDTH_TYPE = "high",
			CLK0_DIVIDE_BY = 2,
			CLK0_MULTIPLY_BY = 25,
			CLK1_DIVIDE_BY = 10,
			CLK1_MULTIPLY_BY = 25,
			CLK2_DIVIDE_BY = 10,
			CLK2_DUTY_CYCLE = 20,
			CLK2_MULTIPLY_BY = 25,
			DPA_DIVIDE_BY = 2,
			DPA_MULTIPLY_BY = 25,
			INCLK0_INPUT_FREQUENCY = 10000,
			OPERATION_MODE = "no_compensation"
		);
...

Let me know if this is working. Normally it should compile and synthesize now. Bust when you'll run the generated chaining_dma testbench in ModelSim it will run but you'll get messages telling you again : CLK0_DIVIDE_BY should be more then '0'.

I'm not really sure if it's a 100 % solution ...