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Altera_Forum
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15 years ago

PCIe Compiler Serdes pll

Hi! I have a problem with the PCIe Compiler: I add the PCIe IP in my quartus IV project (with the SOPC builder, later with the MegaWizard) and add exernal Pins to "refclk", "rx_in0" and "tx_ou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi!

Thank you for the tip, but when i compile the example (chaining_dma) i get the same errors: 

Error: PLL "PCIe_example_chaining_pipen1b:core|PCIe_plus:ep_plus|PCIe:epmap|PCIe_serdes:serdes|PCIe_serdes_alt_c3gxb_0eb8:PCIe_serdes_alt_c3gxb_0eb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0
Error: PLL "PCIe_example_chaining_pipen1b:core|PCIe_plus:ep_plus|PCIe:epmap|PCIe_serdes:serdes|PCIe_serdes_alt_c3gxb_0eb8:PCIe_serdes_alt_c3gxb_0eb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk1_multiply_by and/or clk1_divide_by are either unspecified or set to 0
Error: PLL "PCIe_example_chaining_pipen1b:core|PCIe_plus:ep_plus|PCIe:epmap|PCIe_serdes:serdes|PCIe_serdes_alt_c3gxb_0eb8:PCIe_serdes_alt_c3gxb_0eb8_component|altpll:pll0|altpll_ld81:auto_generated|pll1" has port CLK connected but parameters clk2_multiply_by and/or clk2_divide_by are either unspecified or set to 0
Can you post your settings?