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m_kumar's avatar
m_kumar
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Path Violation in timing analyzer

Hi , Iam working max10 fpga , in timing analyzer i'm getting path violations can i get any help to solve this problem. Report Timing: Found 200 setup paths (200 violated). Worst case slack is -0....
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
5 years ago

Hi Manoj,


Maybe some information (sdc, timing report) to evaluate the issue here needed


  • m_kumar's avatar
    m_kumar
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi sir thanks for the reply i reached the desired timing . Problem was in my sdc file timing values.