Path delay between two nets

Timing analyzer analyse path base on register to register. What you need to do is to add aa bb cc dd as a register and write the correct constrain of it.

Since you are new to timing analysis, my suggestion is to look into the training module here

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

Make sure you click on the follow on courses. Thanks