Forum Discussion
Altera_Forum
Honored Contributor
8 years agoUp to 32-bit integers... I find it a bit odd. They have a parser capable of parsing Verilog numbers so why not use this to parse the expression passed by the set_parameter tcl command.
In Verilog it's possible to use the pre-processor as a work around:module top
`ifdef M_GIT_SHA1
# ( parameter GIT_SHA1 = `M_GIT_SHA1)
`else
# ( parameter GIT_SHA1 = {20{8'h42}})
`endif
( input wire pad_clk_50m_fpga,
And then set: set_global_assignment -name VERILOG_MACRO "M_GIT_SHA1=160'h$sha1"
in the build script, which yields: $./read-gits.sh
GIT_SHA1: 1B15850CADD9D969468FEE6669D86837E7B19239
$git rev-parse HEAD
1b15850cadd9d969468fee6669d86837e7b19239