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Hello,
System Verilog supports using array as a port. We are creating our own component which uses System Verilog. That component is going to be used in Qsys. So, we will need to use hw.tcl file to tell Qsys about our component.
Let me try to elaborate it with one example,
If my port is simply vector ( output logic [31:0] my_data_o ), then I could use following in hw.tcl: add_interface_port my_conduit my_data_o export Output 32.
But if my port is array ( output logic [31:0] my_data__arr_o[1:0] ), how can I declare it in hw.tcl file?
Thank you for your time.
Regards,
Bhaumik
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Unfortunately, but understandably, Qsys only handles 'simple' vectors. You will have to concatenate the two 32 bit elements of your array signal and drive this as a 'output logic [63:0]'. A receiving component then will have to 'unpack' this into an array.
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