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Altera_Forum's avatar
Altera_Forum
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14 years ago

Pass-through logic has been added

Hi, I'm trying to infer a RAM using the following VHDL:

SIGNAL sarray : ramtype; -- ramtype is an array of std_ulogic_vectors

PROCESS (clk)

BEGIN

IF (clk'event AND clk = '1') THEN

out1_data <= sarray(read_address_1);

out2_data <= sarray(read_address_2);

sarray(write_address) <= in_data;

END IF;

END PROCESS;

Which I don't think should have a bypass to return new data in the case that one of the read addresses is the same as the write address, but I get the warning message:

inferred ram node "<name>" from synchronous design logic. pass-through logic has been added to match the read-during-write behavior of the original design.

I can make it go away with the ramstyle attribute, but I want to understand why the compiler would think bypass logic was needed.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Inside the IF you need to tell that if {write enable} then write or else if{read enable} then read. In your code you can read and write data into the RAM at the same time [is it dual port?]. That's the reason why it is adding that logic

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I probably should have included a sentence about how signals work in VHDL. When you assign a value to a signal, it does not update the value of that signal during the current simulation event, it queues the value change to occur after all processing for that event. Since the assignments are inside a process that is only sensitive to the clock, at a clock event, the old array values are being captured for read out prior to the new write data being stored so there should be no combinatorial path through the array regardless of the read and write addresses.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Its a good question, and you're right to correct alteraaditya. It can come down to how the inference works. because you've asked for a true dual port ram (because you have 2x read port) it may be doing something in a specific way, or it could be the chip you're using.

    It is probably worth first reading the HDL coding style guidlines in the altera handbook, followed by raising a mysupport case with altera, as they can be good at pinning down why things happen the way they do.