Pass-through logic has been added

I probably should have included a sentence about how signals work in VHDL. When you assign a value to a signal, it does not update the value of that signal during the current simulation event, it queues the value change to occur after all processing for that event. Since the assignments are inside a process that is only sensitive to the clock, at a clock event, the old array values are being captured for read out prior to the new write data being stored so there should be no combinatorial path through the array regardless of the read and write addresses.