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Altera_Forum
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14 years ago

Parametrized altsyncram using design compiler and quartus

Hi! Is there a way to synthesize an vhdl design that instantiates parametrized altsyncram(s) using Synopsys Design Compiler? Synopsys DC generates black boxes for which all parameters are skip...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I believe DesignWare is a library of IP from Synopsys. I may have the name wrong. It won't help you, I was just mentioning it as a reason you need to keep with DC Compiler. Your reason makes sense.