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Altera_Forum
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14 years ago

Parametrized altsyncram using design compiler and quartus

Hi! Is there a way to synthesize an vhdl design that instantiates parametrized altsyncram(s) using Synopsys Design Compiler? Synopsys DC generates black boxes for which all parameters are skip...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Thank you for your answer.

I'm not fimiliar with DesignWare. Is DesignWare able to execute DC-TCL-synthesis scripts? The reason why I have to stick with DC is because I have to do some changes in the netlist during synthesis. Therefore I source some synthesis scripts which require a GTECH-based netlist/design.