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Altera_Forum's avatar
Altera_Forum
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14 years ago

Parametrized altsyncram using design compiler and quartus

Hi! Is there a way to synthesize an vhdl design that instantiates parametrized altsyncram(s) using Synopsys Design Compiler? Synopsys DC generates black boxes for which all parameters are skip...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I haven't seen anyone use DC synthesis for many years. Note that Synopsys bought Synplify, so they do have an excellent FPGA synthesis tool. If there's something you need like DesignWare support, they might have that integrated. For whatever reason you need to use DC Synthesis, they might be able to provide a better solution that meets those needs.

(As for why their parameters don't get passed to the netlist, I really don't know. If it's just RAMs, inferring them would probably be a better way to go all around, assuming Design Compiler can do this...)