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Thanks corestar and tricky. I forgot about the LPM blocks. I shall definately use the ready made ones. I avoid testbenches as I am not very good with. But I'll put effort. I understand the value of testbenches but they feel abstract at first and never managed to work around the problem. Thanks for the support though.
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You've actually gotten pretty far; you have Modelsim running and are applying stimulus and getting results. You've sort of done half a test bench. You just need the last step of verifying the results. I know it's always tempting to quickly get things running using tools you know (eg Excel), but learning how to verify results in a test bench is not too far beyond what you are already doing.
Not to add another complication, but VHDL is, in my opinion, a horrible simulation language. When it comes to synthesis, VHDL and Verilog are a toss up as to which is the least stupid. For simulation, SystemVerilog is probably far superior to VHDL. Just printing out values is difficult in VHDL. Probably best to stick to VHDL simulation for VHDL code for now though. Tricky is far more knowledgeable in such areas and may have a different opinion.
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