Parallel VHDL

1. Is there anything you're particularly struggling with? This is fairly standard VHDL, but I feel its probably been written this way to be as compact and obfuscated as possible. There are no comments explaining anything, m is a constant in the file with no dependence on generics. There is also some code I dont like - zeros is a signal and not a constant!

If you want to see a diagram, Quartus can provide RTL diagrams and technology mapped (ie. primitives) version via tools -> netlist viewers

2. Unless you're going to do all testing and debugging on chip (very slow, very time consuming) you are going to need a testbench. At a very basic level, the testbench needs to drive the clock and reset, then you need to add in any external stimulus to verify design operation.

Do you have any specific questions?