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You could try using the lpm_shiftreg megafunction. If you're using a schematic design file, double click on a blank area and select it from libraries/megafunctions/storage. Select bus width of 6, serial shift out, parallel data in. Shift direction depends on how you connect up your inputs. You'll need to think about where you get parallel load and clock signals from.
That's one way, at least. Hope it helps.
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Thanks for you help..
Ok.. clock is not a problem, but if i put load = 1 and load = 0 then what is the changes on output ??
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