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Altera_Forum
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17 years ago

Parallel adder timing issues

I am beginner in FPGA design and implementation.I have 2 questions regarding adder implementations. The simulation in below message refers to gate level simulations with SDO file generated by Quartus...
Altera_Forum's avatar
Altera_Forum
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17 years ago

If you're doing a schematic, then megafunctions are probably the way to go, but I think parallel_add is designed more for multiple adders in parallel, then just a single adder. If doing HDL, then when the file is open, Edit -> Insert -> Template has some decent examples.